The need for very large uncooled imaging systems has outpaced the development of large format focal plane arrays (FPAs). This need has motivated approaches to build very large uncooled imaging arrays using smaller arrays mechanically-butted together to form a larger imaging system. Smaller FPAs can be mechanically assembled in close proximity on a common carrier to form a larger imaging array.
Another approach to large format FPAs is reticle stitching. Reticle stitching is directed to producing larger FPAs by sub-dividing a circuitry pattern and then stitching, or recomposing the subfield patterns together using one or more reticles to form a large composite FPA. However, the manufacture of composite FPAs formed by stitching together the interconnections between subfields in accordance with conventional techniques is generally regarded as a problematic process that can provide unacceptably low yields and high costs. Further, the fabrication of sets of reticles which together define an integrated circuit structure constitutes a primary expenditure with regard to the fabrication of integrated circuits, and low reticle yields represent a significant loss of investment.
While buttable array imaging systems can achieve pixel counts that are multiples of the component FPAs with less development effort than a fully-scaled FPA with the same number of pixels, this approach places the burden of development on the chip assembly processes and on the system electronics and software that merge the sub-images. Full-scale large image ROIC and FPA with the same number of pixels require a complex and prolonged development program. Also, the system level performance for full-scale large arrays is only the same as for the component FPAs in a butted system.
A large mechanically-butted FPA imaging array will have some noticeable disadvantages. Notable issues will be in the image itself. There are seams between the component FPAs that result in “seams” in the image that need to be mitigated by image dithering and software. Significantly, in a 2×2 array these seams are in the center of the field of view. The imagery will also have different types of artifacts resulting from sub-sections of the image scanning independently of each other compared to the artifacts of a full array progressive scan. While the large mechanically-butted image array may be cost effective in low volume, the recurring cost of a fully scaled FPA will be lower in high volume production.
Mechanically-butted approaches to very large arrays can start with existing FPA technology, but layout modifications are needed to make an acceptable butted image. Existing FPAs do not lend themselves to being assembled without excessive gaps between the component pixel arrays that will result in seams in the image for which it is difficult to compensate.
With no layout changes, the expected gap between imaging pixels is 2.5 mm plus assembly tolerances.
For mechanically-butted FPA imaging arrays, problem areas of the chip layout include the bond pads, circuitry along the array edges, process test strip and process overhead structures, buffer pixels at the pixel array edges, and the scribe streets. In a standard use, the bond pads are wire bonded to at least three sides of the FPA package. To be a component in a 2×2 butted array, the bond pads must be moved to provide two sides of the chip that are free of bond pads. Another layout issue for a mechanically-butted array is the circuitry along the pixel array edges. If these circuits are left in place, they add approximately 150 μm to the gap between imaging pixels in a mechanically-butted system.
FPAs include “extra” pixels that provide a process buffer at the edge of the pixel array where the pattern abruptly changes from dense pixels to no pixels. This significantly reduces defective pixels at the array edge, improving yield and edge of array image quality. For mechanically-butted systems, if these “extra” pixels are removed to reduce the gap size, there will be significant increases in bad pixels at the component array edges that will reduce yield and reduce image quality in the seam areas of the image.
Another difficult aspect of the FPA floor plan for mechanically-butted arrays is the scribe streets. The scribe streets contain ground busses, chip edge seals, and the actual scribe area to separate die. In all, this exceeds 350 μm on each side of the chip. These are difficult to remove for a mechanically-butted image array as they perform essential functions and the low precision of the dicing process requires a significant space to avoid yield loss from the dicing process, damaging active circuit areas.
Summarizing, a mechanically-butted imaging array is assembled from four FPAs on a common substrate. Both left handed and right handed versions of an optimized ROIC/FPA layout are required for good performance. The bond pads must be removed from the sides that will be butted. The gaps between the imaging pixels are driven by the features on the silicon outside of the live pixel arrays and the mechanical assembly precision.
FIG. 1 provides a table 100 of estimates for the size of gap resulting from each feature or tolerance. The buffer pixels remain for good process quality at the edge of the pixel array. The edge circuits are assumed to be relocated, but the guard ring, edge seal, and scribe lane remain. A minimum physical gap of 25 μm is listed with an additional 100 μm resulting from placement precision, exact scribe location, cleanliness of scribe edge, and parallelism of scribe edge to pixel array.
A need exists for an improved way to assemble a large microbolometer infrared imaging array from sub-arrays without seams or gaps in the resulting image. In particular, there is a need for an easier solution than is available by mechanically-butting sub-arrays on a common substrate or traditional integrated circuit stitching techniques.